The Hardware Side of Cryptography

9 December 2010

Freescale QorIQ P2020 Security Engine : Playing with Controller

Filed under: Co-processor — Tags: , , , , , , — edipermadi @ 8:58 am

Controller is the housekeeping part of Security Engine that enables software to manage the whole security subsystem. The controller part is consisted of 6 64-bits register dealing with interrupt management, identification, status and master control. Each of those 64-bits register are organized in big-endian way.

The identification register enables you to use the same software for various version of SEC machine. The only thing you need is to determine the IP core version and enable / disable some software functionality to match the feature available on the engine.

The interrupt management register (IER, ICR, ISR) enables you to either check, enable or disable interrupt. The following list gives you the supported functionalities :

  • FIFO count rollover
  • Descriptor finished count rollover
  • Data in / out count rollover
  • Timeout
  • Channel done overflow
  • Channel done
  • Channel error
  • Execution unit done
  • Execution unit error

Master Control Register (MCR) enables you to remap, manage priority and reset the whole security engine. Finally, the assignment status register (EUASR) enables you to check whether a particular execution unit is currently assigned to channel or not.

Take a look on the following implementation of those controller registers in C.

typedef struct sec_reg_ctrlr_iex_t
{
    unsigned int rsvd_0   : 8;
    unsigned int FFE_CNT  : 1;  /* Fetch FIFO enqueue count rollover          */
    unsigned int DF_CNT   : 1;  /* Descriptor Finished Count Rollover         */
    unsigned int DI_CNT   : 1;  /* Data In Count Rollover                     */
    unsigned int DO_CNT   : 1;  /* Data Out Count Rollover                    */
    unsigned int rsvd_1   : 3;
    unsigned int ITO      : 1;  /* Internal Time Out                          */
    unsigned int rsvd_2   : 4;
    unsigned int CH4_DNOV : 1;  /* Channel 4 Done Overflow                    */
    unsigned int CH3_DNOV : 1;  /* Channel 3 Done Overflow                    */
    unsigned int CH2_DNOV : 1;  /* Channel 2 Done Overflow                    */
    unsigned int CH1_DNOV : 1;  /* Channel 1 Done Overflow                    */
    unsigned int CH4_ERR  : 1;  /* Channel 4 Error                            */
    unsigned int CH4_DN   : 1;  /* Channel 4 Done                             */
    unsigned int CH3_ERR  : 1;  /* Channel 3 Error                            */
    unsigned int CH3_DN   : 1;  /* Channel 3 Done                             */
    unsigned int CH2_ERR  : 1;  /* Channel 2 Error                            */
    unsigned int CH2_DN   : 1;  /* Channel 2 Done                             */
    unsigned int CH1_ERR  : 1;  /* Channel 1 Error                            */
    unsigned int CH1_DN   : 1;  /* Channel 1 Done                             */
    unsigned int rsvd_3   : 4;
    unsigned int CRCU_ERR : 1;  /* CRCU Error                                 */ 
    unsigned int CRCU_DN  : 1;  /* CRCU Done                                  */
    unsigned int KEU_ERR  : 1;  /* KEU  Error                                 */
    unsigned int KEU_DN   : 1;  /* KEU  Done                                  */
    unsigned int STEU_ERR : 1;  /* STEU Error                                 */
    unsigned int STEU_DN  : 1;  /* STEU Done                                  */
    unsigned int PKEU_ERR : 1;  /* PKEU Error                                 */
    unsigned int PKEU_DN  : 1;  /* PKEU Done                                  */
    unsigned int rsvd_4   : 2;
    unsigned int RNG_ERR  : 1;  /* RNGU Error                                 */
    unsigned int RNG_DN   : 1;  /* RNGU Done                                  */
    unsigned int rsvd_5   : 2;
    unsigned int AFEU_ERR : 1;  /* AFEU Error                                 */
    unsigned int AFEU_DN  : 1;  /* AFEU Done                                  */
    unsigned int rsvd_6   : 2;
    unsigned int MDEU_ERR : 1;  /* MDEU Error                                 */
    unsigned int MDEU_DN  : 1;  /* MDEU Done                                  */
    unsigned int rsvd_7   : 2;
    unsigned int AESU_ERR : 1;  /* AESU Error                                 */
    unsigned int AESU_DN  : 1;  /* AESU Done                                  */
    unsigned int rsvd_8   : 1;
    unsigned int DEU_ERR  : 1;  /* DEU  Error                                 */
    unsigned int DEU_DN   : 1;  /* DEU  Done                                  */
} SEC_REG_CTRLR_IEX_T;

typedef struct sec_reg_ctrlr_id_t
{
    unsigned int IP_ID    : 16; /* IP block identifier                        */
    unsigned int IP_MJ    :  8; /* IP Major revision number                   */
    unsigned int IP_MN    :  8; /* IP Minor revision number                   */
    unsigned int rsvd_0   :  8;
    unsigned int IP_INT   :  8; /* IP block integration options               */
    unsigned int rsvd_1   :  8;
    unsigned int IP_CFG   :  8; /* IP block configuration options             */
} SEC_REG_CTRLR_ID_T;

typedef struct sec_reg_ctrlr_euasr_t
{
    unsigned int rsvd_0 : 4;
    unsigned int AFEU   : 4;    /* AFEU Assignment Status Register            */
    unsigned int rsvd_1 : 4;
    unsigned int MDEU   : 4;    /* MDEU Assignment Status Register            */
    unsigned int rsvd_2 : 4;
    unsigned int AESU   : 4;    /* AESU Assignment Status Register            */
    unsigned int rsvd_3 : 4;
    unsigned int DEU    : 4;    /* DEU  Assignment Status Register            */
    unsigned int rsvd_4 : 8;
    unsigned int CRCU   : 4;    /* CRCU Assignment Status Register            */
    unsigned int rsvd_5 : 4;
    unsigned int STEU   : 4;    /* STEU Assignment Status Register            */
    unsigned int PKEU   : 4;    /* PKEU Assignment Status Register            */
    unsigned int rsvd_6 : 4;
    unsigned int RNGU   : 4;    /* RNGU Assignment Status Register            */
} SEC_REG_CTRLR_EUASR_T;

typedef struct sec_reg_ctrlr_mcr_t
{
    unsigned int rsvd_0          : 16;
    unsigned int RCA1            :  1;  /* Remap Channel Address 1            */
    unsigned int RCA2            :  1;  /* Remap Channel Address 2            */
    unsigned int RCA3            :  1;  /* Remap Channel Address 3            */
    unsigned int RCA4            :  1;  /* Remap Channel Address 4            */
    unsigned int rsvd_1          :  2;
    unsigned int PRIORITY        :  2;  /* Priority on Master Bus             */
    unsigned int rsvd_2          :  6;
    unsigned int GIH             :  1;  /* Global Inhibit                     */
    unsigned int SWR             :  1;  /* Software Reset                     */
    unsigned int CHN3_EU_PR_CNT  :  8;  /* Channel 3 EU Priority Count        */
    unsigned int CHN4_EU_PR_CNT  :  8;  /* Channel 4 EU Priority Count        */
    unsigned int CHN3_BUS_PR_CNT :  8;  /* Channel 3 Bus Priority Count       */
    unsigned int CHN4_BUS_PR_CNT :  8;  /* Channel 4 Bus Priority Count       */
} SEC_REG_CTRLR_MCR_T;

typedef struct sec_reg_ctrlr_t{
    SEC_REG_CTRLR_IEX_T   IER;      /* Interrupt Enable Register              */
    SEC_REG_CTRLR_IEX_T   ISR;      /* Interrupt Status Register              */
    SEC_REG_CTRLR_IEX_T   ICR;      /* Interrupt Clear Register               */
    SEC_REG_CTRLR_ID_T    ID;       /* Identification Register                */
    SEC_REG_CTRLR_EUASR_T EUASR;    /* EU Assignment Status Register          */
    SEC_REG_CTRLR_MCR_T   MCR;      /* Master Control Register                */
}SEC_REG_CTRL_T;

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